Synthesis of Self-Checking Combination Devices Based on Allocating Special Groups of Outputs

被引：2

作者：

Efanov, D. V. ^{[1
,2
]}

Sapozhnikov, V. V. ^{[3
]}

Sapozhnikov, Vl. V. ^{[3
]}

机构：

[1] LocoTech Signal LLC, Moscow, Russia

[2] Russian Univ Transport, Moscow, Russia

[3] Emperor Alexander I St Petersburg State Transport, St Petersburg, Russia

来源：

AUTOMATION AND REMOTE CONTROL | 2018年 / 79卷 / 09期

关键词：

combination device; self-checking check circuit; independent outputs; unidirectionally independent outputs; unidirectionally and asymmetrically independent outputs; parity code; Berger's code; code with the detection of double errors; ERROR-DETECTION SYSTEMS; INDEPENDENT OUTPUTS; PARITY CODES; CIRCUITS; DESIGN;

D O I：

10.1134/S0005117918090060

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

We propose a new structure of a self-checking combinational device where, based on the properties of parity and Berger codes, as well as a code with the detection of all double errors in information vectors, the problem of detecting all single faults of logical elements can be solved without transforming the structure of the source device. The properties of binary codes with the detection of all double errors that can be used in constructing the proposed structure are considered. We give an example of constructing a new structure.

引用

页码：1609 / 1620

页数：12

共 26 条

[1] Aksenova G. P., 2008, DATA PROBL UPRAVLEN, V5, P62
[2] [Anonymous], 2006, CODE DESIGN DEPENDAB
[3] [Anonymous], P 14 IEEE E W DES TE
[4] Parity driven reconfigurable duplex system
Borecky, Jaroslav
Kohlik, Martin
Kubatova, Hana
[J]. MICROPROCESSORS AND MICROSYSTEMS, 2017, 52 : 251 - 260
[5] SELF-CHECKING COMBINATIONAL CIRCUIT-DESIGN FOR SINGLE AND UNIDIRECTIONAL MULTIBIT ERROR
BUSABA, FY
LALA, PK
[J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1994, 5 (01): : 19 - 28
[6] Sum Codes with Efficient Detection of Twofold Errors for Organization of Concurrent Error-Detection Systems of Logical Devices
Dmitriev, V. V.
Efanov, D. V.
Sapozhnikov, V. V.
Sapozhnikov, Vl. V.
[J]. AUTOMATION AND REMOTE CONTROL, 2018, 79 (04) : 665 - 678
[7] Conditions for detecting a logical element fault in a combination device under concurrent checking based on Berger's code
Efanov, D. V.
Sapozhnikov, V. V.
Sapozhnikov, Vl. V.
[J]. AUTOMATION AND REMOTE CONTROL, 2017, 78 (05) : 891 - 901
[8] On summation code properties in functional control circuits
Efanov, D. V.
Sapozhnikov, V. V.
Sapozhnikov, Vl. V.
[J]. AUTOMATION AND REMOTE CONTROL, 2010, 71 (06) : 1117 - 1123
[9] Synthesis of low power CED circuits based on parity codes
Ghosh, S
Basu, S
Touba, NA
[J]. 23RD IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2005, : 315 - 320
[10] Goessel M, 1997, AUTOMAT REM CONTR+, V58, P299

← 1 2 3 →