Design of Networks on Chips for 3D ICs

被引：0

作者：

Murali, Srinivasan ^{[1
,2
]}

Benini, Luca ^{[3
]}

De Micheli, Giovanni ^{[2
]}

机构：

[1] iNoCs, Lausanne, Switzerland

[2] Ecole Polytech Fed Lausanne, LSI, Lausanne, Switzerland

[3] Univ Bologna, DEIS, Bologna, Italy

来源：

2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010) | 2010年

关键词：

SYSTEMS;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Three-dimensional integrated circuits, where multiple silicon layers are stacked vertically have emerged recently. The 3D ICs have smaller form factor, shorter and efficient use of wires and allow integration of diverse technologies in the same device. The use of Networks on Chips (NoCs) to connect components in a 3D chip is a necessity. In this short paper, we present an outline on designing application-specific NoCs for 3D ICs.

引用

页码：164 / +

页数：2

共 4 条

[1] 3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration [J].

Banerjee, K ;

Souri, SJ ;

Kapur, P ;

Saraswat, KC .

PROCEEDINGS OF THE IEEE, 2001, 89 (05) :602-633

[2]

De Micheli G., 2006, NETWORKS CHIPS TECHN

[3]

Guerrier P., 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537), P250, DOI 10.1109/DATE.2000.840047

[4]

Seiculescu C, 2009, DES AUT TEST EUROPE, P9

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