A novel dual-modulus 2.8 GHz divide-by-127/128 prescaler using pull down transistor in 0.35 μm CMOS technology

被引：0
作者：
Rana, RS [1 ]
机构：
[1] Inst Microelect, Integrated Circuits & Syst Lab, Singapore 117685, Singapore
来源：
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2005年 / 42卷 / 02期
关键词：
prescaler; CMOS; dual-modulus; filp-flop; PLL; counter;
D O I：
10.1007/s10470-005-5754-0
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Design of high divide-by-value dual-modulus prescaler remains a challenge in CMOS realization for high speed operation. Prior arts for dual modulus prescaler either divide by a low divide-by-value or cannot operate at high speed. The proposed topology is suitable for high divide-by-value operation at high speed.
引用
收藏
页码：191 / 195
页数：5
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