Wafer deposition/metallization and back grind, process-induced warpage simulation

During deposition/metallization processes, metal interconnects and dielectric films are layered on top of the wafer. Wafer warpage appears due to the mismatch in thermal expansion coefficients of the various deposited materials, as well as intrinsic stresses. Large warpage is one of the root causes of failures occurring during backside grind process and subsequent processes. Wafers are routinely thinned by backside grind prior to dicing to aid the sawing operation, improve heat transfer, or reduce Rdson, and to allow the final assembled package thickness to be minimized. As the wafer thickness is decreased during backside grind the wafer progressively become less able to support its own weight and to resist the stresses generated by front side dielectric and metal deposition. Therefore, modeling the wafer warpage during the dielectric and metal deposition process and the backside grind is important to achieve optimal wafer and die yield. A FEA approach is developed to simulate both wafer deposition and backside grind processes. During the deposition processes, the multi-layer thin film depositions are modeling with different temperatures by non-linear finite element in both geometry and materials is presented. The residual warpage and stress results from the deposition phases are used as the initial warpage and stress for the backside grind process. Advanced element death and birth techniques are used to simulate the deposition/metallization process and grind process layer by layer.