Wakeup-Free and Endurance-Robust Ferroelectric Field-Effect Transistor Memory Using High Pressure Annealing

被引：56

作者：

Manh-Cuong Nguyen ^{[1
]}

Kim, Sihyun ^{[2
,3
]}

Lee, Kitae ^{[2
,3
]}

Yim, Ji-Yong ^{[1
]}

Choi, Rino ^{[1
]}

Kwon, Daewoong ^{[4
]}

机构：

[1] Inha Univ, Dept Mat Sci & Engn, Incheon 22212, South Korea

[2] Seoul Natl Univ, Dept Elect & Comp Engn, Seoul 08826, South Korea

[3] Seoul Natl Univ, Interuniv Semicond Res Ctr, Seoul 08826, South Korea

[4] Inha Univ, Dept Elect Engn, Incheon 22212, South Korea

来源：

IEEE ELECTRON DEVICE LETTERS | 2021年 / 42卷 / 09期

基金：

新加坡国家研究基金会;

关键词：

FeFETs; Logic gates; Threshold voltage; Annealing; Tin; Voltage measurement; Transistors; Ferroelectric FET (FeFET); HZO; endurance characteristics of FeFET; high-pressure annealing; TRANSIENT NEGATIVE CAPACITANCE; FEFETS; FET;

D O I：

10.1109/LED.2021.3096248

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Wakeup-free and endurance-robust HfZrO2 (HZO) ferroelectric field-effect transistor (FeFET) was fabricated on a silicon-on-insulator substrate. After a high-pressure forming gas annealing as the last alloy step, the performance and endurance of the FeFETs were significantly improved by trap states reduction, polarization enhancement, and wake-up elimination. As the result, the FeFETs show superior endurance exceeding 10(10) cycles and robust retention behavior at program/erase biases of +/- 3.5V and pulse width of 100 ns. These results indicate that appropriate thermal treatment for the interlayer and ferroelectric material could substantially improve FeFET performance and reliability.

引用

页码：1295 / 1298

页数：4

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