Theory and practical implementation of harmonic resonant rail driver

被引：1

作者：

Moon, JS ^{[1
]}

Athas, WC ^{[1
]}

Beerel, PA ^{[1
]}

机构：

[1] Univ So Calif, Los Angeles, CA 90089 USA

来源：

ISLPED'01: PROCEEDINGS OF THE 2001 INTERNATIONAL SYMPOSIUM ON LOWPOWER ELECTRONICS AND DESIGN | 2001年

关键词：

harmonic-resonant rail driver; energy-recovery circuit; pulse-forming network; clock generation;

D O I：

10.1109/LPE.2001.945392

中图分类号：

TE [石油、天然气工业]; TK [能源与动力工程];

学科分类号：

0807 ; 0820 ;

摘要：

This paper presents a new algorithm for designing efficient harmonic resonant rail drivers. The circuit solution is coupled to a standard pulse source and uses only discrete passive components. It can thus be externally tuned to minimize the consumed power in the target IC. A new efficient algorithm based on current-fed pulse-forming network theory is proposed to find the value of each discrete component for a target frequency and a given load capacitance. The proposed driver topology can be used to generate any desired periodic 50% duty-cycle waveform by superimposing multiple harmonics of the desired waveform, however, this paper focuses on the generation of square-wave clock signals. We have tested the driver with a capacitive load between 38.3pF and 97.8pF. The overall dissipation for our second-order harmonic rail driver is 19% of fCV(2) at 15MHz and 97.8pF load.

引用

页码：153 / 158

页数：6

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