Dual-k Spacer Device Architecture for the Improvement of Performance of Silicon n-Channel Tunnel FETs

被引：67

作者：

Virani, Hasanali G. ^{[1
,2
]}

Adari, Rama Bhadra Rao ^{[1
]}

Kottantharayil, Anil ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, Bombay 400076, Maharashtra, India

[2] Goa Coll Engn, Dept Elect & Telecommun Engn, Farmagudi Goa, India

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2010年 / 57卷 / 10期

关键词：

Band-to-band tunneling; high-k; subthreshold slope; tunnel field-effect transistor; FIELD-EFFECT TRANSISTOR; GATE; DESIGN;

D O I：

10.1109/TED.2010.2057195

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A dual-k spacer concept is proposed and evaluated in underlap and nonunderlap n-channel silicon tunnel field-effect transistors (FETs) for the first time using extensive device simulations. The dual-k spacer consists of an inner layer made of a high-k material and an outer layer made of a low-k material. It is shown that the dual-k spacer improves the performance of n-channel tunneling FETs and more so for the underlap structures. Performance improvements are illustrated and explained for SiO2, Al2O3, and HfO2 gate dielectrics. The structure is optimized for the ON-state current without degrading the OFF-state current or the subthreshold slope.

引用

页码：2410 / 2417

页数：8

共 36 条

[1]

[Anonymous], P DEV RES C JUN

[2] Band-to-band tunneling in carbon nanotube field-effect transistors [J].

Appenzeller, J ;

Lin, YM ;

Knoch, J ;

Avouris, P .

PHYSICAL REVIEW LETTERS, 2004, 93 (19) :196805-1

[3] Lateral interband tunneling transistor in silicon-on-insulator [J].

Aydin, C ;

Zaslavsky, A ;

Luryi, S ;

Cristoloveanu, S ;

Mariolle, D ;

Fraboulet, D ;

Deleonibus, S .

APPLIED PHYSICS LETTERS, 2004, 84 (10) :1780-1782

[4] A NEW 3-TERMINAL TUNNEL DEVICE [J].

BANERJEE, S ;

RICHARDSON, W ;

COLEMAN, J ;

CHATTERJEE, A .

IEEE ELECTRON DEVICE LETTERS, 1987, 8 (08) :347-349

[5] Vertical tunnel field-effect transistor with bandgap modulation and workfunction engineering [J].

Bhuwalka, KK ;

Schulze, J ;

Eisele, I .

ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2004, :241-244

[6]

BHUWALKA KK, 2005, THESIS U BUNDESWEHR

[7] Double-gate tunnel FET with high-κ gate dielectric [J].

Boucart, Kathy ;

Mihai Ionescu, Adrian .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (07) :1725-1733

[8] Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec [J].

Choi, Woo Young ;

Park, Byung-Gook ;

Lee, Jong Duk ;

Liu, Tsu-Jae King .

IEEE ELECTRON DEVICE LETTERS, 2007, 28 (08) :743-745

[9] ZENER AND AVALANCHE BREAKDOWN IN AS-IMPLANTED LOW-VOLTAGE SI N-P JUNCTIONS [J].

FAIR, RB ;

WIVELL, HW .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1976, 23 (05) :512-518

[10] INSULATED GATE TUNNEL JUNCTION TRIODE [J].

HOFSTEIN, SR ;

WARFIELD, G .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1965, ED12 (02) :66-&

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