Efficient Design of Rounding Based Static Segment Imprecise Multipliers for Error Tolerance Application

Error-Tolerant applications regularly accomplish more data adaption. Approximate computing is one of the optimum strategies for data manipulation in several Error-Tolerant applications. It depletes circuit complexity and enhances area, power, and latency design parameters. Moreover, multiplication is a vital operation in Error-Tolerant applications. Existing Exact Multipliers are used in the approximate computing approach to expand the design parameters with fewer accuracy parameters in the present scenario. Hence, in this paper, new Rounding Based Static Segment Imprecise Multipliers (RBSSIM0, RBSSIM1) with and without Estimator Logic Circuit (ELC) are proposed to ameliorate the design and accuracy parameters. ELC removes lower-order important information in the input of bit length. Imprecise multiplication is executed using a rounding unit and barrel shifter in the proposed RBSSIM designs. These multipliers are synthesized and simulated using Cadence RTL compiler, Xilinx Vivado, and MATLAB with input bit sizes ranging from 8-bit to 32-bit. The results evidenced RBSSIM depletion area, delay, power, and energy by an average of 61.1%, 29.8%, 54.9%, and 64.2%, respectively, compared to existing imprecise multipliers. In addition to that, the proposed RBSSIM has better performance in terms of accuracy parameters. RBSSIM has improved NED, MRED, MED, and WCE on an average of 14.12%, 39.1%, 42.12%, and 24.21%, respectively. As a final point, RBSSIM provides higher SSIM and PSNR over the existing imprecise multipliers after including in the Error-Tolerant applications.