Cascaded multilevel inverter based on symmetric-asymmetric DC sources with reduced number of components

被引:86
作者
Saeedian, Meysam [1 ]
Adabi, Jafar [1 ]
Hosseini, Seyyed Mehdi [1 ]
机构
[1] Babol Noshirvani Univ Technol, Fac Elect & Comp Engn, Babol Sar, Iran
关键词
VOLTAGE-SOURCE INVERTER; TOPOLOGY; CONVERTERS; IMPLEMENTATION; REDUCTION; DESIGN;
D O I
10.1049/iet-pel.2017.0039
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This study presents a new module for multilevel inverters with reduced components. Each module produces 25 levels using four asymmetrical DC voltage sources (two 1V(DC) and two 5V(DC) sources) and 10 semiconductor switches. A significant advantage of the suggested module is its potentiality in producing voltage levels with negative polarity without any end side H-bridge inverter. Therefore, switches with lower voltage ratings are used in its structure. Series connection of the proposed structure leads to a modular topology which produces more voltage levels using reasonable number of switches, gate driver circuits, power diodes and less DC voltage sources. These advantages are analysed by comparing this structure with other state-of-the-art topologies. Selective harmonic elimination pulse width modulation (SHE-PWM) scheme is used to achieve output voltage with high quality. To produce all voltage levels, two algorithms are proposed to determine DC voltage sources magnitude. The accuracy of the suggested module performance in producing all voltage levels is verified by simulation and experimental results.
引用
收藏
页码:1468 / 1478
页数:11
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