A Column-and-Row-Parallel CMOS Image Sensor with Thermal and 1/f Noise Suppression Techniques

A CMOS image sensor architecture is presented that uses an extra level of parallelism and thermal and 1/f noise suppression techniques to achieve both low-light detection and a high frame rate. By adding the row-parallel readout ADCs, the conversion speed is improved by more than twice compared to the conventional top-bottom parallel ADC structure. The thermal and 1/f noise is reduced by combining the intrinsic oversampling of the incremental sigma-delta ADCs and the 1/f noise suppression through the source-follower inversion-to-accumulation method. A 128x128 pixel CMOS image sensor with 5mmx5mm chip dimension has been fabricated in a 180nm CIS technology to validate the architecture. The measured noise is 128 mu V at the equivalent line time of 2.5 mu s in digital CDS mode, with the total power consumption of 60mW. In the 1/f noise suppression mode with the same condition, the total noise is as low as 118 mu V.