THE CONFIGURABLE AND HIGH-PERFORMANCE ARCHITECTURE DESIGN OF 2D IN-PLACE IDWT IN JPEG2000

被引：0

作者：

Han Jinheng ^{[1
]}

Lu Song ^{[1
]}

Wang Jinxiang ^{[1
]}

Xu Weizhe ^{[1
]}

Fu Fangfa ^{[1
]}

机构：

[1] Harbin Inst Technol, Microelect Ctr, Harbin 150001, Peoples R China

来源：

2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT) | 2014年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A multi-level 2D-IDWT's architecture with high performance and memory efficiency is proposed. The proposed architecture is composed of two ID-IDWT cores and one single rearrangement register. Both the ID-IDWT cores take only one multiplier delay in their critical path at the throughput rate of one-inputlone-output. The single register, rather than traditional 1.5N transposing memory, is used to complete rearrangement task. The pipeline architecture of 2D-IDWT takes only one multiplier in the critical path. Moreover, the proposed architecture reduces 27% on-chip memory(only need 2N for 53-IDWT and 4N for 97-IDWT) by utilizing the proposed alternate scanning method and decreases 20% off-chip memory by applying the proposed memory map strategy without any performance loss.

引用

页数：3

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