THE CONFIGURABLE AND HIGH-PERFORMANCE ARCHITECTURE DESIGN OF 2D IN-PLACE IDWT IN JPEG2000

A multi-level 2D-IDWT's architecture with high performance and memory efficiency is proposed. The proposed architecture is composed of two ID-IDWT cores and one single rearrangement register. Both the ID-IDWT cores take only one multiplier delay in their critical path at the throughput rate of one-inputlone-output. The single register, rather than traditional 1.5N transposing memory, is used to complete rearrangement task. The pipeline architecture of 2D-IDWT takes only one multiplier in the critical path. Moreover, the proposed architecture reduces 27% on-chip memory(only need 2N for 53-IDWT and 4N for 97-IDWT) by utilizing the proposed alternate scanning method and decreases 20% off-chip memory by applying the proposed memory map strategy without any performance loss.