Comparison of Massive-Parallel and FFT-Based Acquisition Architectures for GNSS Receivers

One of the most important characteristic in performance evaluation and comparison of mass-market receivers is the Time-To-First-Fix (TTFF). Taking a closer look at the architecture of state-of-the-art receivers, it can be observed that mainly two different approaches are followed to decrease TTFF: Either, correlators are massively parallelized or FFT-based techniques for fast convolution are used. For that reason, this contribution addresses a detailed comparison of the two approaches on hardware level for a 90 nm standard-cell CMOS-technology. The main focus is to provide a detailed cost-benefit analysis that enables a reasonable choice of the acquisition architecture. Costs in this context consider silicon chip area on the standard-cell CMOS-technology. Benefit refers to the acquisition speed and accuracy. In detail, the paper is structured as follows: First, common building blocks are introduced and parameterized. These blocks are used to prepare the digital input signal for acquisition. Afterwards, two different approaches for computing a convolution of the prepared input signal and a local code are briefly described on algorithmic level. While the massive-parallel approach is comparatively straight forward (it can simply be derived from standard tracking channel architectures in common receivers), the FFT-based approach is more complex. Here, the impact of the required FFT-lengths and the word-lengths in the data-path are of major concern. The final design of an FFT based on fixed point arithmetic is a non trivial task since the word-lengths always depend on the application. In the final section of the paper, costs of both acquisition architectures are compared.