Flip chip assembly process development, reliability assessment and process characterization for polymer stud grid array-chip scale package

被引：0

作者：

Paydenkar, CS ^{[1
]}

Jefferson, FG ^{[1
]}

Baldwin, DF ^{[1
]}

机构：

[1] Georgia Inst Technol, George W Woodruff Sch Mech Engn, Mfg Res Ctr, AdAPT Adv Assembly Proc Technol Lab, Atlanta, GA 30332 USA

来源：

51ST ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE | 2001年

关键词：

D O I：

10.1109/ECTC.2001.927869

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

The Polymer Stud Grid Array (PSGA) package is a new and unique type of area array chip scale package that shows significant advantages over conventional package configurations by virtue of its high potential for miniaturization and process cost saving potential. This paper focuses on two key elements of PSGA technology which are: 1) developing a high throughput flip chip assembly process technology for PSGA-CSP configurations using existing Surface Mount Technology (SMT), and 2) qualifying the reliability performance of flip chip PSGA packages. The flip chip interconnection system evaluated is eutectic lead-tin solder. Various flip chip strategies are screened based on underfill materials and associated flip chip process technology. The underfill materials selected for evaluation are no flow reflowable, fast flow snap cure encapsulants, and high performance underfill systems. This work discusses issues related to developing a robust high throughput flip chip assembly process and presents preliminary reliability based on air-to-air thermal cycling (-55 degreesC to 125 degreesC) of the assembled PSGA Chip Scale Packages (CSPs).

引用

页码：782 / 789

页数：8