An Efficient Residue-to-Binary Converter for the New Moduli Set {2n/2 ± 1, 22n+1, 2n+1}

被引：0

作者：

Siewobr, Hillary ^{[1
]}

Gbolagade, Kazeem A. ^{[2
]}

Cotofana, Sorin ^{[3
]}

机构：

[1] Univ Dev Studies, Fac Math Sci, Dept Comp Sci, Navrongo, Ghana

[2] Kwara State Univ, Coll Informat & Comm Tech, Dept Comp Lib & Informat Sci, Malete, Kwara State, Nigeria

[3] Delft Univ Technol, Comp Engn Lab, Delft, Netherlands

来源：

2014 14TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC) | 2014年

关键词：

Residue Number System; Reverse Converter; Moduli Set; Mixed Radix Conversion; Chinese Remainder Theorem; 4-MODULI SUPERSET 2(N)-1; REVERSE CONVERTER; 2(N+1)-1;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a new four moduli set {2(n/2) +/- 1, 2(2n+1), 2(n) + 1} is proposed together with a two level Chinese Remainder Theorem (CRT) based reverse converter for efficient residue number system arithmetic. The CRT is simplified to obtain a converter that is cheaper and faster than the best known state of the art converters. Experimental results obtained from FPGA implementation suggest that on average, the proposed converter is 27.96% and 21.68% better than the state of the art converter for the moduli set {2(n), 2(n/2) - 1, 2(n/2) + 1, 2(2n+1) - 1} interms of area and delay, respectively. Additionally, when compared with the state of the art area and speed efficient converters for the {2(n), 2(n) - 1, 2(n) + 1, 2(n+1) - 1} moduli set, the proposed converter improved delay by 68.76% and 55.16% and area by 65.05% and 71.35%, respectively.

引用

页码：508 / 511

页数：4

共 19 条

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