An Architecture for Near-Data Processing Systems

被引：3
|
作者：
Vermij, Erik [1 ]
Hagleitner, Christoph [2 ]
Fiorin, Leandro [1 ]
Jongerius, Rik [1 ]
van Lunteren, Jan [2 ]
Bertels, Koen [3 ]
机构：
[1] IBM Res, Delft, Netherlands
[2] IBM Res Zurich, Zurich, Switzerland
[3] Delft Univ Technol, Delft, Netherlands
来源：
PROCEEDINGS OF THE ACM INTERNATIONAL CONFERENCE ON COMPUTING FRONTIERS (CF'16) | 2016年
关键词：
D O I：
10.1145/2903150.2903478
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
Near-data processing is a promising paradigm to address the bandwidth, latency, and energy limitations in today's computer systems. In this work, we introduce an architecture that enhances a contemporary multi-core CPU with new features for supporting a seamless integration of near-data processing capabilities. Crucial aspects such as coherency, data placement, communication, address translation, and the programming model are discussed. The essential components, as well as a system simulator, are realized in hardware and software. Results for the important Graph500 benchmark show a 1.5x speedup when using the proposed architecture.
引用
收藏
页码：357 / 360
页数：4
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