FPGA and ASIC implementation of reliable and effective architecture for a LTE downlink transmitter

Hardware implementation of LTE-Advanced systems using FPGA and ASIC technology is a highly promising technology. This article proposed a reliable and effective architecture for a LTE downlink transmitter under different antenna configurations including SISO 1x1; MIMO 2x2. The design has been synthesized using Altera Quartus II 13.1.4 on Altera Stratix-V 5SGSMD8K2F4012. The parameter improving cost is introduced to evaluate the upgrading of resources caused by performance improvement. With this proposed structure, improving cost can be reduced compared with traditional method. The proposed plan is fabricated as an ASIC using SMIC 55-nm CMOS technology. Finally, the design is demonstrated in the test platform, showing a successful performance.