A Reconfigurable High-speed Spiral FIR Filter Architecture

The need for efficient Finite Impulse Response (FIR) filters in high-speed applications targets Field Programmable Gate Arrays (FPGAs) as an effective and flexible platform for digital implementation. Although FIR filter offer advantages like linear phase characteristic, no feedback loops and good system stability, its convolution nature poises a challenge in parallelization due to data dependency and computational complexity. To resolve this, we propose a novel FPGA-based reconfigurable filter architecture, which processes several data samples in parallel and breaks down data interdependency in a spiral fashion. This generic pipelined-parallel filter is parameterizable in terms of filter order and degree of parallelization. Experimental results show a throughput of 7.2 GSPS with an operating frequency of only 450 MHz for a filter length of 11 with 16 parallel inputs. With parallelization of 4, it is 4.64 times faster than the state-of- the-art solution for a filter length of 16 and a promising 41% increase in throughput is achieved for a higher order of 61.