A High-Speed FIR Adaptive Filter Architecture using a Modified Delayed LMS Algorithm

被引:0
|
作者
Meher, Pramod K. [1 ]
Maheshwari, Megha [2 ]
机构
[1] Inst Infocomm Res, Dept Embedded Syst, Singapore, Singapore
[2] Nanyang Technol Univ, Sch Technol Engn, Singapore, Singapore
关键词
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暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we present a modified delayed least means square (DLMS) adaptive algorithm to achieve lower adaptation-delay. Besides, we have proposed an efficient pipelined architecture for the implementation of this adaptive filter. We have shown that the proposed DLMS adaptive filter can be implemented by a pipelined inner-product computation unit for calculation of feedback error, and a pipelined weight-update unit consisting of N parallel multiply accumulators, for filter order N. From the synthesis results we find that the existing direct-form structure of [8] involves nearly 50% more area-delay product (ADP) and nearly 74% more energy per sample (EPS) than the proposed one, in average, for filter orders N = 8, 16 and 32. The best of the existing systolic structures [7], similarly, involves nearly 43% more ADP and nearly 35% higher EPS than the proposed one for the same filter orders.
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页码:121 / 124
页数:4
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