Evaluating the cache architecture of multicore processors

被引：4

作者：

Tao, Jie ^{[1
]}

Kunze, Marcel ^{[1
]}

Karl, Wolfgang ^{[2
]}

机构：

[1] Karlsruhe Inst Technol, Steinbuch Ctr Comp, Karlsruhe, Germany

[2] Karlsruhe Inst Technol, Inst Tech Informat, Karlsruhe, Germany

来源：

PROCEEDINGS OF THE 16TH EUROMICRO CONFERENCE ON PARALLEL, DISTRIBUTED AND NETWORK-BASED PROCESSING | 2008年

关键词：

cache performance; multicore processor; simulation; OpenMp application;

D O I：

10.1109/PDP.2008.22

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Microprocessor architecture for both commercial and academical purpose is coming into a new generation: multiprocessors on a chip. Together with this novel architecture, questions and research topics also arise. For example, how to design the on-chip caches to avoid memory operations becoming the performance bottleneck? In this work, we study the impact of various cache architectures on the execution behavior of multi-threading applications. We focus on four general design issues: cache structure, configuration parameters, coherence influence, and prefetching strategies. The study is based on a self-developed cache simulator that models the functionality of a multicore cache hierarchy with arbitrary levels and various organizations. The achieved results can direct both hardware and program developers to optimize their cache designs or the program codes.

引用

页码：12 / +

页数：2

共 12 条

[1] SimpleScalar: An infrastructure for computer system modeling [J].

Austin, T ;

Larson, E ;

Ernst, D .

COMPUTER, 2002, 35 (02) :59-+

[2]

BENITEZ D., 2006, P 3 C COMP FRONT CF, P361

[3]

GIBSON J, 2000, P 9 INT C ARCH SUPP, P49

[4]

Jin H., 1999, Technical Report NAS-99-011

[5]

Liu C, 2004, 10TH INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS, P176

[6]

MAGNUSSON PS, 1995, P 8 ANN SIM S PHOEN

[7]

Modarressi M., 2006, Canadian Conference on Electrical and Computer Engineering (CCECE) 2006, P959

[8] Data cache prefetching using a global history buffer [J].

Nesbit, KJ ;

Smith, JE .

IEEE MICRO, 2005, 25 (01) :90-97

[9]

NETHERCOTE N, 2003, P 3 WORKSH RUNT VER

[10]

VANDERWIEL S, 1997, IEEE COMPUT, V30, P23

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