Automatic Abstraction of Combinational Logic Circuit from Scanned Document Page Images

Information extraction from scanned document page images is an important issue in image analysis. The main objectives of this work are: vectorization of image of the digital logic-gate circuits as graph, and automatic generation of Boolean expression. We have employed a novel method for circuit component separation using morphological operators. Connecting wires (in the form of poly lines in the image) lead to adjacency matrix describing directed interconnection between logic gates. Logic gate symbols are recognized by support vector machine (SVM) based on the features obtained by deep convolutional neural network (DCNN). Finally, we exploit this abstract representation of digital logic circuit as a graph to determine the Boolean expression. The approach is tested on a dataset developed by us and the results are encouraging.