A Σ-Δ fractional-N frequency synthesizer using a wideband integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications

被引：7
|
作者：
Lee, HI [1 ]
Cho, JK [1 ]
Lee, KS [1 ]
Hwang, IC [1 ]
Ahn, TW [1 ]
Nah, KS [1 ]
Park, BH [1 ]
机构：
[1] Samsung Elect Co Ltd, Device Solut Network, Syst LSI Div, RF Analog PT, Yongin 449711, Gyeonggi Do, South Korea
来源：
ESSCIRC 2003: PROCEEDINGS OF THE 29TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2003年
关键词：
D O I：
10.1109/ESSCIRC.2003.1257081
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A fractional-N frequency synthesizer (FNFS) in 0.5-um SiGe BiCMOS technology is implemented. In order to operate wideband frequency range, a switched capacitor bank LC tank VCO and an Adaptive Frequency Calibration (AFC) technique are used. A 3-bit 4th order T-A modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3Hz as well as agile switching time. The experimental results show -80dBc/Hz in-band phase noise within the loop bandwidth of 25kHz and -129dBclHz out-of-band phase noise at 400kHz-offset frequency. The fractional spurious is less than -70dBclHz at 300kHz offset frequency and the reference spur is -75dBclHz. The lock time is less than 150 As. The proposed synthesizer consumes 19.5mA from a single 2.8-V supply voltage and meets the requirements of GSM/GPRS/WCDMA applications.
引用
收藏
页码：97 / 100
页数：4
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