Design of Low Jitter Phase-Locked Loop with Closed Loop Voltage Controlled Oscillator

This paper presents a novel phase- locked loop (PLL) architecture to generate a low jitter output clock with a closed loop voltage controlled oscillator (VCO). The proposed closed loop VCO consists of an open loop VCO, an integrator, a non- overlapping clock generator and a switched- capacitor resistor. Because the closed loop VCO has a high- pass characteristic for a VCO noise transfer function and a negative feedback loop suppresses a phase noise of the open loop VCO, the closed loop VCO shows the low phase noise compared to the conventional open loop VCO. Moreover, the closed loop VCO can filter any perturbation at the control voltage due to a low-pass characteristic of input voltage transfer function. We design the proposed PLL scheme in 130 nm low power eM OS technology at 1.5V supply. An integrated jitter is 5.81 psec at 300 MHz output frequency, which is 24% smaller than the jitter of previous PLL with the open loop VCO. The proposed PLL consumes 4.8 mW at 400 MHz output frequency.