Novel designs of a carry/borrow look-ahead adder/subtractor using reversible gates

被引：8

作者：

Rahmati, Maryam ^{[1
]}

Houshmand, Monireh ^{[1
]}

Kaffashian, Masoud Houshmand ^{[2
]}

机构：

[1] Imam Reza Int Univ, Dept Elect Engn, Mashhad, Iran

[2] Payame E Noor Univ, Dept Elect Engn, Mashhad, Iran

来源：

JOURNAL OF COMPUTATIONAL ELECTRONICS | 2017年 / 16卷 / 03期

关键词：

Reversible circuit; Carry-look-ahead adder; Quantum cost; Garbage output; Constant input; CIRCUITS; LOGIC;

D O I：

10.1007/s10825-017-1031-6

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Reversible logic has received great attention in recent years due to its ability to reduce power consumption. Reversible logic improves energy efficiency, velocity of nano-circuits and the portability. We can construct irreversible circuits using reversible gates. Adders are one of the most important elements of digital circuits. Among all different types of adders, carry-look-ahead adder is the fastest. This paper presents new designs of a reversible carry-look-ahead adder with better performance compared to the existing designs, then using 2's complement method, a reversible carry/borrow look-ahead adder/subtractor is designed. The proposed designs are simulated by VHDL, and the results are compared to the existing designs.

引用

页码：856 / 866

页数：11

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