Low-error carry-free fixed-width multipliers and their application to DCT/IDCT

被引：0
|
作者：
Juang, TB [1 ]
Hsiao, SF [1 ]
Kuang, SR [1 ]
Tsai, MY [1 ]
机构：
[1] Natl Sun Yat Sen Univ, Dept Comp Sci & Engn, Kaohsiung 80424, Taiwan
来源：
PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2: SOC DESIGN FOR UBIQUITOUS INFORMATION TECHNOLOGY | 2004年
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D O I：
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中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, we propose a low-error fixed-width redundant multiplier design. The design is based on the statistical analysis of the value of the truncated partial products in binary signed-digit representation with modified Booth encoding. The overall truncation error is significantly reduced with negligible hardware overhead. Simulation on DCT/IDCT of images with 256 gray levels shows our proposed multiplication design has higher PSNR/SNR.
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页码：457 / 460
页数：4
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