Low-power digital filtering using approximate processing

被引：77
|
作者：
Ludwig, JT [1 ]
Nawab, SH [1 ]
Chandrakasan, AP [1 ]
机构：
[1] BOSTON UNIV,KNOWLEDGE BASED SIGNAL PROC GRP,BOSTON,MA 02215
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1996年 / 31卷 / 03期
关键词：
D O I：
10.1109/4.494201
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We present an algorithmic approach to the design of low-power frequency-selective digital filters based on the concepts of adaptive filtering and approximate processing. The proposed approach uses a feedback mechanism in conjunction with well-known implementation structures for finite impulse response (FIR) and infinite impulse response (IIR) digital filters; Our algorithm is designed to reduce the total switched capacitance by dynamically varying the filter order based on signal statistics. A factor of 10 reduction in power consumption over fixed-order filters is demonstrated for the filtering of speech signals.
引用
收藏
页码：395 / 400
页数：6
相关论文
共 50 条
  • [41] Low-power analog image processing using transform imagers
    Hasler, P
    Bandyopadhyay, A
    Anderson, DV
    PROCEEDINGS OF THE 2002 IEEE 10TH DIGITAL SIGNAL PROCESSING WORKSHOP & 2ND SIGNAL PROCESSING EDUCATION WORKSHOP, 2002, : 333 - 338
  • [42] Reliable low-power digital signal processing via reduced precision redundancy
    Shim, BY
    Sridhara, SR
    Shanbhag, NR
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12 (05) : 497 - 510
  • [43] A novel reconfigurable architecture of low-power unsigned multiplier for digital signal processing
    Quan, S
    Qiang, Q
    Wey, CL
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 3327 - 3330
  • [44] Low-power digital signal processing via dynamic algorithm transformations (DAT)
    Goel, M
    Shanbhag, NR
    CONFERENCE RECORD OF THE THIRTY-SECOND ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1 AND 2, 1998, : 1204 - 1208
  • [45] LOW-POWER ELECTROMECHANICAL DIGITAL READOUT
    BEKE, WSM
    MIDDELHOEK, S
    IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 1977, 23 (02) : 166 - 174
  • [46] DESIGNING LOW-POWER DIGITAL CMOS
    BLAIR, GM
    ELECTRONICS & COMMUNICATION ENGINEERING JOURNAL, 1994, 6 (05): : 229 - 236
  • [47] Face Processing on Low-Power Devices
    Ardizzone, Edoardo
    La Cascia, Marco
    Morana, Marco
    PROCEEDINGS OF THE 2009 FOURTH INTERNATIONAL CONFERENCE ON EMBEDDED AND MULTIMEDIA COMPUTING, 2009, : 186 - 191
  • [48] LOW-POWER CMOS DIGITAL DESIGN
    CHANDRAKASAN, AP
    SHENG, S
    BRODERSEN, RW
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (04) : 473 - 484
  • [49] Low-Power FPGA Design Using Memoization-Based Approximate Computing
    Sinha, Sharad
    Zhang, Wei
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (08) : 2665 - 2678
  • [50] Design and Analysis of Low-Power and High Speed Approximate Adders Using CNFETs
    Bhargav, Avireni
    Huynh, Phat
    SENSORS, 2021, 21 (24)
12345