Correlated Dual-Loop Sturdy MASH Continuous-Time Delta-Sigma Modulators

被引:10
作者
Park, Beomsoo [1 ,2 ]
Han, Changsok [3 ]
Maghari, Nima [1 ,2 ]
机构
[1] Univ Florida, Dept Elect & Comp Engn, Gainesville, FL 32611 USA
[2] Qualcomm Inc, San Diego, CA 92121 USA
[3] Marvell Semicond Inc, Santa Clara, CA 95054 USA
关键词
Multi-stage noise shaping; Computer architecture; Stability criteria; Modulation; Circuit stability; Delays; Quantization (signal); Analog-to-digital converters (ADCs); continuous time (CT); correlated loops; delta-sigma modulator (DSM); multi-loop noise shaping; sturdy MASH (SMASH); MHZ-BW; ADC; DESIGN; DB; CALIBRATION; BANDWIDTH;
D O I
10.1109/JSSC.2022.3186079
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This article presents a new multi-loop delta-sigma modulator (DSM) structure that combines the advantages of both the traditional multi-stage noise shaping (MASH) and sturdy MASH (SMASH) architectures. It removes the need for an explicit quantization error extraction digital-to-analog converter (DAC) typically required in multi-loop structures, which allows to eliminate the delay mismatch problem related to the intrinsic propagation delay of the first loop quantizer. The proposed architecture essentially uses the SMASH architecture as its core and has similar characteristics. However, it further simplifies the structure allowing to remove all the feedback DACs in the cascaded loop. The prototype DSM fabricated in a 65-nm process achieves signal-to-noise-and-distortion ratio (SNDR) and dynamic range (DR) of 73.4 and 78.3 dB, respectively, in an 18.75-MHz bandwidth. With 1.1/1.5-V (1.5 V for DAC) supply voltage, the prototype DSM consumes 17.85 mW at 600-MHz operating speed corresponding to a Walden and Schreier figure of merits (FOMs) of 124.1 fJ/conv-step and 168.6 dB (using DR result), respectively.
引用
收藏
页码:2934 / 2943
页数:10
相关论文
共 26 条
[1]   Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback [J].
Baluni, Alok ;
Pavan, Shanthi .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 56 (03) :729-738
[2]  
Bano F., 2019, Pharmaceuticals and Personal Care Products: Waste Management and Treatment Technology, P1, DOI DOI 10.1016/B978-0-12-816189-0.00001-9
[3]   A 2.2 GHz Continuous-Time ΔΣ ADC With-102 dBc THD and 25 MHz Bandwidth [J].
Breems, Lucien ;
Bolatkale, Muhammed ;
Brekelmans, Hans ;
Bajoria, Shagun ;
Niehof, Jan ;
Rutten, Robert ;
Oude-Essink, Bert ;
Fritschij, Franco ;
Singh, Jagdip ;
Lassche, Gerard .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2016, 51 (12) :2906-2916
[4]   A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS [J].
Dong, Yunzhi ;
Zhao, Jialin ;
Yang, Wenhua ;
Caldwell, Trevor ;
Shibata, Hajime ;
Li, Zhao ;
Schreier, Richard ;
Meng, Qingdong ;
Silva, Jose B. ;
Paterson, Donald ;
Gealow, Jeffrey C. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2016, 51 (12) :2917-2927
[5]   A Continuous-Time 0-3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS [J].
Dong, Yunzhi ;
Yang, William ;
Schreier, Richard ;
Sheikholeslami, Ali ;
Korrapati, Sudhir .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2014, 49 (12) :2868-2877
[6]   A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS [J].
Edward, Alexander ;
Liu, Qiyuan ;
Briseno-Vidrios, Carlos ;
Kinyua, Martin ;
Soenen, Eric G. ;
Karsilayan, Aydin Ilker ;
Silva-Martinez, Jose .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017, 52 (02) :448-459
[7]   A CT 2-2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction [J].
Fukazawa, Mitsuya ;
Oshima, Takashi ;
Fujiwara, Masaki ;
Tateyama, Katsuki ;
Ochi, Atsushi ;
Alsubaie, Raed ;
Matsui, Tetsuo .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 56 (10) :2943-2955
[8]   A Fast Computation Method for The Satellite-to-site Visibility [J].
Han, Chao ;
Yang, Pengbin ;
Wang, Xiaohui ;
Liu, Shenggang .
2018 IEEE CONGRESS ON EVOLUTIONARY COMPUTATION (CEC), 2018, :2461-2468
[9]  
He T, 2018, ISSCC DIG TECH PAP I, P230, DOI 10.1109/ISSCC.2018.8310268
[10]   A 4th-Order Continuous-Time Delta-Sigma Modulator Using 6-bit Double Noise-Shaped Quantizer [J].
Kim, Taewook ;
Han, Changsok ;
Maghari, Nima .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017, 52 (12) :3248-3261