Front-end readout system for PHENIX RICH

被引：0

作者：

Tanaka, Y ^{[1
]}

Hara, H

Ebisu, K

Hibino, M

Matsumoto, T

Sakaguchi, T

Kikuchi, J

Winterberg, AL

Walker, JW

Frank, S

Moscone, C

Jones, JP

Young, GR

Oyama, K

Hamagaki, H

机构：

[1] Nagasaki Inst Appl Sci, Nagasaki 8510193, Japan

[2] Waseda Univ, Tokyo 1698555, Japan

[3] Oak Ridge Natl Lab, Oak Ridge, TN 37831 USA

[4] Univ Tokyo, CNS, Tokyo 1880002, Japan

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2000年 / 47卷 / 06期

关键词：

D O I：

10.1109/23.903835

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A front-end readout system with a custom backplane and custom circuit modules has been developed for the RICH subsystem of the PHENIX experiment. The design specifications and test results of the backplane and the modules are presented in this paper. In the module design, flexibility for modification is maximized through the use of Complex Programmable Logic Devices. In the backplane design, a source-synchronous bus architecture is adopted for the data and control bus. The transfer speed of the backplane has reached 640 Mbyte/s with a 128-bit data bus. Total transaction time is estimated to be less than 30 mus per event when this system is used in the experiment. This result indicates that the performance satisfies the data-rate requirement of the PHENIX experiment.

引用

页码：1995 / 2002

页数：8

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