Parallel Computation Using DSP Slices in FPGA

被引：1

作者：

Unnikrishnan, Supriya K. ^{[1
]}

Madhavan, Sudheesh ^{[2
]}

机构：

[1] Toc H Inst Sci & Technol, ECE Dept, Kochi, Kerala, India

[2] Tecnode Solut Pvt Ltd, Bangalore, Karnataka, India

来源：

INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ENGINEERING, SCIENCE AND TECHNOLOGY (ICETEST - 2015) | 2016年 / 24卷

关键词：

FPGA; DSP; Parallel Processing;

D O I：

10.1016/j.protcy.2016.05.064

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

The sophistication of applications and hunger for high quality digital data demands increase in the processing power. High performance signal processing is possible only though parallelism. At the same time, flexibility and scalability are the need of the hour due to dynamically changing standards and design up gradation. This paper describes an implementation of the computational framework using the DSP Slices in the FPGA. The customized instructions will provide the computation flexibility whereas specialized DSP macros in FPGA ensure high performance. (C) 2016 The Authors. Published by Elsevier Ltd.

引用

页码：1127 / 1134

页数：8

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