Performance Analysis of III-V and IV Semiconductors Based Double Gate Hetero Material Negative Capacitance TFET

被引：6

作者：

Rajan, Chithraja ^{[1
]}

Paul, Omdarshan ^{[1
]}

Samajdar, Dip Prakash ^{[1
]}

Hidouri, Tarek ^{[2
]}

Nasr, Samia ^{[3
]}

机构：

[1] PDPM Indian Inst Informat Technol Design & Mfg, Micro & Nano Computat Lab, Elect & Commun Engn Discipline, Jabalpur, Madhya Pradesh, India

[2] Univ Monastir, Fac Sci Monastir, Dept Phys, Microoptoelect & Nanostruct Lab,LR99ES29, St Environm, Monastir 5019, Tunisia

[3] King Khalid Univ, Fac Sci, Dept Phys, Adv Funct Mat & Optoelect Lab AFMOL, POB 9004, Abha, Saudi Arabia

来源：

SILICON | 2022年 / 14卷 / 14期

关键词：

Negative capacitance; Ferroelectric; Subthreshold slope; Band-to-band tunneling (BTBT); Potential intensification; Physically doped; TFET; LOW-POWER; TUNNEL FET; SCHEME;

D O I：

10.1007/s12633-022-01667-x

中图分类号：

O64 [物理化学（理论化学）、化学物理学];

学科分类号：

070304 ; 081704 ;

摘要：

In this paper, a combination of ferroelectric (FE) HfZrO2 and dielectric (DE) SiO2 is used to generate negative capacitance (NC) effects in Hetero Material (HM) tunnel FETs (TFETs). We have investigated the performance of some III-V alloys and Group IV semiconductors along with the FE-DE gate stack. The electric field at the tunnel junction adequately improved due to potential intensification in the presence of NC that leads to reduced threshold voltage (V-th). Also, a suitable combination of low and high band gap III-V and IV semiconductors in the source and drain/channel regions improves ON current (I-ON) and subthreshold swing (SS) significantly as compared to the conventional TFET device. Here we present a comparison of DC/RF/linearity analysis among a wide variety of NC-HM-TFETs, which is not reported previously to the best of our knowledge. We found that Ge/GaAs based device provides better I-ON/I-OFF = 1.95 x 10,(13) V-th = 0.41, SS =12.2 mV/dec, g(m) = 47.7 mu S and f(t) = 4.89GHz after final device optimization, which concludes higher energy proficiency and superior performance in comparison to conventional TFET.

引用

页码：8529 / 8541

页数：13

共 35 条

[11] Study of circuit performance and non quasi static effect in germanium tunnel FET for different temperatures [J].

Ghosh, Sayani ;

Koley, Kalyan ;

Sarkar, Chandan K. .

MICROELECTRONICS JOURNAL, 2019, 90 :204-210

[12] Supply and threshold voltage scaling for low power CMOS [J].

Gonzalez, R ;

Gordon, BM ;

Horowitz, MA .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (08) :1210-1216

[13] RF analysis and temperature characterization of pocket doped L-shaped gate tunnel FET [J].

Goswami, Partha Pratim ;

Khosla, Robin ;

Bhowmick, Brinda .

APPLIED PHYSICS A-MATERIALS SCIENCE & PROCESSING, 2019, 125 (10)

[14] Analytical model of a novel double gate metal-infused stacked gate-oxide tunnel field-effect transistor (TFET) for low power and high-speed performance [J].

Guha, Sourav ;

Pachal, Prithviraj ;

Ghosh, Sudipta ;

Sarkar, Subir Kumar .

SUPERLATTICES AND MICROSTRUCTURES, 2020, 146

[15] Simulation-based study of negative capacitance double-gate junctionless transistors with ferroelectric gate dielectric [J].

Jiang, Chunsheng ;

Liang, Renrong ;

Wang, Jing ;

Xu, Jun .

SOLID-STATE ELECTRONICS, 2016, 126 :130-135

[16]

Kao J, 1997, DES AUT CON, P409, DOI 10.1145/266021.266182

[17] Negative Capacitance for Boosting Tunnel FET performance [J].

Kobayashi, Masaharu ;

Jang, Kyungmin ;

Ueyama, Nozomu ;

Hiramoto, Toshiro .

IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2017, 16 (02) :253-258

[18]

Kumar S., 2018, 15 IEEE IND COUNC C, P1

[19] Negative Capacitance FET With 1.8-nm-Thick Zr-Doped HfO2 Oxide [J].

Kwon, Daewoong ;

Cheema, Suraj ;

Shanker, Nirmaan ;

Chatterjee, Korok ;

Liao, Yu-Hung ;

Tan, Ava J. ;

Hu, Chenming ;

Salahuddin, Sayeef .

IEEE ELECTRON DEVICE LETTERS, 2019, 40 (06) :993-996

[20]

Lee M.H., 2013, 2013 IEEE Int. Electron Devices Meet, V4, p5.1, DOI [DOI 10.1109/IEDM.2013.6724561, 10.1109/IEDM.2013.6724561]

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