An Optimized Compression Strategy for Compressor-based Approximate Multiplier

Approximate multipliers have recently attracted great attention due to their substantially lower energy consumption and area overhead. But previous approximate multiplier designs are mainly focused on the design of approximate compressors, little attention is paid to the compression strategy of partial product matrix. This paper proposes an optimized universal compression scheme for the compressor-based approximate multiplier. When we apply the new compression scheme to the state-of-the-art compressors, the accuracy of the approximate multiplier is largely increased and fewer exact adders are needed. To prove the efficiency of the new compression strategy, an 8-bit and a 12-bit approximate multipliers are designed using Verilog and synthesized under the TSMC 40-nm CMOS technology. Compared to the state-of-the-art, the experimental results indicate that the mean error distance of 8-bit multiplier decreases by 19.6%, with area and power reduced by 5.38% and 2.38% respectively; 12-bit multiplier has a reduction of 18.1% for mean error distance, with area and power reduced by 6.29% and 3.24% respectively. Moreover, application to image processing is presented, which shows that the proposed approximate multiplier has a better performance.