Variation Tolerant Design of a Vector Processor for Recognition, Mining and Synthesis

Variations have emerged as one of the most significant challenges facing the design of integrated circuits in nanoscale technologies. As a consequence, variation tolerant design has become essential at all levels of design abstraction. In this work, we investigate the design of a variation tolerant vector processor for applications from the emerging domains of recognition, mining and synthesis (RMS). We demonstrate how leveraging domain-specific application and architectural characteristics can lead to new and highly effective variation tolerance mechanisms. A predominant fraction of the processing elements in the target processor perform vector reduction operations, which leads to two key properties that we exploit for variation tolerance. First, the circuit delay of a processing element can be bounded a few cycles in advance based on its micro-architectural state. Second, vector reduction operations may be decomposed by performing operations on smaller vectors and combining the partial results. These properties allow us to create a joint hardware software variation tolerance mechanism, wherein the hardware is enhanced with the ability to predict timing errors during the execution of vector instructions and effectively preempt their occurrence, while software is tasked with restoring the correct outputs. We enhance the proposed scheme with a dynamic voltage control mechanism that further improves energy efficiency by exploiting variations in data characteristics seen across different applications. Our experiments on six RMS applications demonstrate that the proposed variation tolerant design technique achieves an average of 32% energy improvement over a traditional guardband based design.