Power based Single-phase PLL with in-loop Fix Delay Filter under Distortion

被引：0
|
作者：
Xie, Menxi [1 ]
He, Liqun [2 ]
Fan, Mingdi [2 ]
Yang, Yong [2 ]
机构：
[1] Soochow Univ, Inst Intelligent Struct & Syst, Suzhou, Peoples R China
[2] Soochow Univ, Sch Rail Transportat, Suzhou, Peoples R China
来源：
2020 IEEE 9TH INTERNATIONAL POWER ELECTRONICS AND MOTION CONTROL CONFERENCE (IPEMC2020-ECCE ASIA) | 2020年
基金：
中国国家自然科学基金;
关键词：
Phase-Locked Loop; Single-phase System; Fix Delay Filter; ALGORITHMS;
D O I：
10.1109/IPEMC-ECCEAsia48364.2020.9367690
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Precise voltage phase information is of great importance for grid-connected converter control. For single-phase system, product-type based Power Phase-Locked Loop (pPLL) has high order disturbs in phase detector when the grid voltage is distorted. To obtain zero steady state phase detected error, this paper presents a cascade fix delay filter applied in loop of pPLL. The configuration of cascade filter unit is analyzed, also the parameter design guidelines and digital implementation of the methods are provided. The simulation and experimental tests are carried out to verify the correctness and effectiveness of the filter.
引用
收藏
页码：1338 / 1342
页数：5
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