Signal word-level statistical properties-based activation approach for hardware Trojan detection in DSP circuits

被引:4
作者
Li, He [1 ]
Liu, Qiang [1 ]
Chen, Fuqiang [1 ]
机构
[1] Tianjin Univ, Sch Microelect, Tianjin Key Lab Imaging & Sensing Microelect Tech, Tianjin 300072, Peoples R China
基金
中国国家自然科学基金;
关键词
integrated circuit testing; digital signal processing chips; statistical analysis; integrated circuit design; correlation methods; invasive software; trigger HTs; test vectors; autocorrelation; standard deviation; existing activation approach; internal rare nodes; DSP circuit design; bit-level transition activity; digital signal processing circuits; HT detection process; circuit functional failure; low transition bits; hardware Trojan detection; signal word-level statistical properties-based activation approach; DESIGN;
D O I
10.1049/iet-cdt.2018.5101
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Hardware Trojan (HT), which usually is activated under rare conditions associated with low transition bits in a circuit, can lead to circuit functional failure or information leakage. Effectively activating hidden HTs is a major challenge during the HT detection process. In this study, the authors propose a novel approach for efficiently activating Trojans hidden in digital signal processing (DSP) circuits by increasing the transition activity of rare bits. In particular, the bit-level transition activity can be increased by controlling signal word-level statistical properties, such as standard deviation and autocorrelation, and their propagation through various operators involved in DSP circuit design. As a result, the proposed approach can generate appropriate test vectors, which effectively activate internal rare nodes and trigger HTs. The experimental results show that using the proposed approach the transition activity of rare bits is significantly increased and various HTs inserted into DSP circuits are activated with reduced time. By comparing to an existing activation approach working at the bit level, the proposed approach is superior in test vectors generation time up to 9 times reduction and HT activation time up to 66 times reduction.
引用
收藏
页码:258 / 267
页数:10
相关论文
共 35 条
[1]  
[Anonymous], 2010, P 2010 IEEE INT WORK
[2]  
[Anonymous], 2017 INT S CIRC SYST
[3]  
[Anonymous], EMBEDDED SYSTEMS LET
[4]  
[Anonymous], INT WORKSH CRYPT HAR
[5]  
[Anonymous], ACM T EMBEDDED COMPU
[6]   A Novel Sustained Vector Technique for the Detection of Hardware Trojans [J].
Banga, Mainak ;
Hsiao, Michael S. .
22ND INTERNATIONAL CONFERENCE ON VLSI DESIGN HELD JOINTLY WITH 8TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, 2009, :327-332
[7]   Hardware Trojan Attacks: Threat Analysis and Countermeasures [J].
Bhunia, Swarup ;
Hsiao, Michael S. ;
Banga, Mainak ;
Narasimhan, Seetharam .
PROCEEDINGS OF THE IEEE, 2014, 102 (08) :1229-1247
[8]  
Çakir B, 2015, DES AUT TEST EUROPE, P471
[9]   IP protection of DSP algorithms for system on chip implementation [J].
Chapman, R ;
Durrani, TS .
IEEE TRANSACTIONS ON SIGNAL PROCESSING, 2000, 48 (03) :854-861
[10]   Abstraction of word-level linear arithmetic functions from bit-level component descriptions [J].
Dasgupta, P ;
Chakrabarti, PP ;
Nandi, A ;
Krishna, S .
DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS, 2001, :4-8