An FPGA-based Priority Packet Queues

被引：1

作者：

Smekal, David ^{[1
]}

Nemeth, Frantisek ^{[1
]}

Dvorak, Jan ^{[1
]}

机构：

[1] Brno Univ Technol, Fac Elect Engn & Commun, Tech 12, Brno, Czech Republic

来源：

IFAC PAPERSONLINE | 2019年 / 52卷 / 27期

关键词：

Packet Queues; Quality of Service; Shaping Throughput; Limiter; Tocken Bucket; VHDL; FPGA; Netcope Development Kit; SYSTEM;

D O I：

10.1016/j.ifacol.2019.12.689

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Paper deals with issues and problems of packet queue management in high speed packet networks. Design implementation is made in VHDL hardware description language. In this paper, the design of limiter mechanism for Quality of Service (QoS) is performed. The article present the full description of the architecture, the simulation results and the results of the practical implementation on the NFB-200G2QL network cards based on the Xilinx Virtex UltraScale+ chip and works at 200 MHz. Various parameterized designs were synthesized to provide a comparative study with other implementations in FPGA technology. (C) 2019, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

引用

页码：377 / 381

页数：5

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