Optimizing sequential verification by retiming transformations

Sequential verification methods based on reachability analysis are still limited by the size of the BBDs involved in computations. Extending their applicability to larger and larger and real circuits is still a key issue. Within this framework, we explore a new way to improve symbolic traversal performance, working on the representation of state sets. We exploit retiming to reduce the number of latches of a FSM, and to re-locate them in order to obtain a simplified state set representation. We consider retiming as a temporary state space transformation to increase the efficiency of sequential verification. We discuss it as a state space transformation and we formally analyze the conditions under which such a transformation is equivalence preserving for a given property under verification. We lower image computation cost, and we reduce the size of BBDs representing intermediate results and state sets. Experimental results show considerable memory and time improvements on some benchmark and home made circuits.