Design technique for mitigation of alpha-particle-induced single-event transients in combinational logic

Alpha particles incident on CMOS integrated circuits deposit charges on circuit nodes resulting in single-event transients (SETs). These transient errors propagate through the circuit and reach a latch where they may get latched under proper conditions. This paper presents circuit design techniques to remove the effects of such SET pulses from the circuit. An optimized design is developed whose area, power, and speed performance is superior to other design methods for SET mitigation. Simulation results showing SET pulse elimination are presented.