An Extended Building-In Reliability Methodology on Evaluating SRAM Reliability by Wafer-Level Reliability Systems

被引:6
作者
Chien, Wei-Ting Kary [1 ]
Hao, Feng [2 ]
机构
[1] Centrill Technol, Corp Mfg SVP, Hsinchu 30288, Taiwan
[2] Semicond Mfg Int Corp, Qual & Reliabil Ctr, Shanghai 201203, Peoples R China
关键词
Semiconductor device reliability; Random access memory; Integrated circuit reliability; Reliability engineering; Stress; Aging; Building-in reliability; process reliability; wafer-level reliability; product reliability; SRAM; package-level reliability;
D O I
10.1109/TDMR.2020.2964999
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Advancement in integrated circuit (IC) brings a series of challenges on product reliability. In order to meet these challenges and fulfill customers' requirements, we introduced the methodology of building-in reliability (BIR) into whole stages during IC manufacturing. The wafer-level reliability (WLR) is an essential element of the BIR system. Significant amount of costs, resources, and times are saved from the early detections on reliability deficiencies at design and development stages. After successful mass production, hidden reliability risks can also be timely identified before shipment. Currently, the process reliability has been successfully evaluated by WLR platform. However, the product reliability, which covers much wider reliability factors, has not been effectively covered by WLR. Currently, we still rely on the conventional package-level reliability (PLR) tests to assess product reliability. In this paper, we report how the classical static random access memory (SRAM) is transplanted into the WLR system, which serves as an efficient platform to detect reliability weakness. In our extended BIR methodology, by reasonable test structure and pattern designs, proper electric parameters selections, test methods optimizations, we can thoughtfully consider inherent failure mechanisms and process fluctuations in order to build quantitative reliability models, which are essential to our proposed system. The quantitative reliability model was not seen in the similar WLR approaches and this may explain why these previous proposals failed. Finally, we report the obtained robust correlations between single-bit cell wear-out and package-level SRAM degradations, which is further validated by conventional HTOL tests. Our approaches provide opportunities not only on early detecting reliability weakness, but also on reliability assurance after product deliveries. These two contributions are essential and especially crucial for advanced technology developments.
引用
收藏
页码:106 / 118
页数:13
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