Impacts of HLS Optimizations on Side-Channel Leakage for AES Circuits

被引：0

作者：

Mizuno, Takumi ^{[1
]}

Zhang, Qidi ^{[1
]}

Nishikawa, Hiroki ^{[1
,2
]}

Kong, Xiangbo ^{[1
]}

Tomiyama, Hiroyuki ^{[1
]}

机构：

[1] Ritsumeikan Univ, Grad Sch Sci & Engn, Kusatsu, Shiga, Japan

[2] Japan Soc Promot Sci, Tokyo, Japan

来源：

18TH INTERNATIONAL SOC DESIGN CONFERENCE 2021 (ISOCC 2021) | 2021年

关键词：

AES; High-Level-Synthesis; optimizations; T-test;

D O I：

10.1109/ISOCC53507.2021.9613900

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Many IoT devices have been compromised by side-channel attacks. Among them, power analysis attack is a well-known technique to reveal the secret key of a circuit by measuring the power of the target device. In this study, we investigate the relationship between the performance and the side-channel attack resistance of cryptographic circuits. We synthesize AES circuits from a behavioral description written in the C language and analyze the power. In order to evaluate tolerance to side-channel attacks, we conduct T-test for the power consumed on the circuit. Experimental results show that there appears a trade-off between the side-channel leakage and the performance of the circuit.

引用

页码：53 / 54

页数：2

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