A digital CMOS design technique for SEU hardening

被引：86

作者：

Baze, MP ^{[1
]}

Buchner, SP

McMorrow, D

机构：

[1] Boeing Co, Seattle, WA 98124 USA

[2] SFA Inc, Largo, MD 20785 USA

[3] USN, Res Lab, Washington, DC 20375 USA

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2000年 / 47卷 / 06期

关键词：

D O I：

10.1109/23.903815

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new cell design technique is described which may be used to create SEU hardened circuits. The technique uses actively biased, isolated well transistors to prevent transients in combinational logic from reaching the output node.

引用

页码：2603 / 2608

页数：6

共 12 条

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