The effect of post-deposition anneal in O-2 at different temperatures (500-700 degreesC) on the microstructure and electrical properties of SiO2/ZrO2 gate dielectric stacks is investigated. It is shown that the as-deposited ZrO2 layers are partly amorphous and crystallize after post-deposition anneal. From the analysis of high-frequency capacitance-voltage (C-V) characteristics, positive (negative) fixed charge is found in the as-deposited layer when Al (Au) electrodes are used. Furthermore, positive charge is generated in the gate stack and the density of interface states is increased during post-deposition anneal in O-2. Both positive charge and interface state density can be greatly reduced by an additional post-metallization anneal in H-2 at low temperature (400 degreesC). The dielectric constant of the gate stack presents a large increase after O-2 post-deposition anneal at 700 degreesC, which may be attributed to the partial transformation of the silicon oxide interfacial layer into a Zr silicate. The leakage current through the gate stack is reduced by several orders of magnitude after O-2 annealing, consistent with the increase in SiOx layer thickness, as well as the reduction in bulk trap density revealed by the reduced hysteresis effect observed in the C-V characteristics. The temperature dependence of the current density through the gate stack is also reduced after the post-deposition anneal in O-2, which is attributed to the reduction in the trap-assisted tunnelling contribution to the leakage current.
