Transient Latchup in Power Analog Circuits

被引：0

作者：

Vashchenko, V. A. ^{[1
]}

LaFonteese, D. ^{[1
]}

Concannon, A. ^{[1
]}

机构：

[1] Natl Semicond Corp, Santa Clara, CA USA

来源：

2011 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2011年

关键词：

ESD; latchup; TLP; power; analog;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Two cases of transient latchup specific to power management analog integrated circuit design are described and analyzed experimentally. The representative case studies include the interaction of a power array and ESD clamp and the interaction of two high voltage ESD clamps

引用

页数：4