Total ionizing dose effects on n-channel metal oxide semiconductor transistors with annular-gate and ring-gate layouts

Two-edged-gate, annular-gate and ring-gate N-channel metal oxide semiconductor (NMOS) transistors with two different values of gate oxide thickness (t(ox)) are fabricated in a commercial 0.35 mu m complementary metal oxide semiconductor (CMOS) process. The tests for the total ionizing dose (TID) effects of the transistors are carried out with a total dose up to 2000 Gy(Si). The results show that the dependence of radiation-induced threshold voltage shift on t(ox) is larger than the power-law t(ox)(3). The TID tolerance of the low voltage NMOS (t(ox) = 11 nm) is improved from 300 Gy(Si) to over 2000 Gy(Si) by the annular-gate or ring-gate layout. For the high voltage NMOS (t(ox) = 26 nm), the annular-gate or ring-gate layout can only mitigate the growth of the off-state leakage current when the total dose is less than 1000 Gy(Si). As radiation hardening techniques, the annular-gate and ring-gate layouts have similar effects, but the annular-gate layout is slightly more effective in terms of the radiation-induced threshold voltage shift and off-state leakage current increase. The test results are theoretically explained by examining and analyzing the experimental data.