Analysis of Challenges for On-Chip Optical Interconnects

Optical interconnects are touted as the solution to the performance bottleneck of future interconnects in scaled technology nodes. Though significant strides have been made in realizing silicon photonic devices that can give high performance in controlled lab environments, there still exist technical challenges preventing dense integration and reliability in widely varying conditions. This paper examines such problems while suggesting possible solution space and proposing some alternatives. We also calculate the actual power advantage that optical links will have compared to an electrical link while considering the thermal stabilization and other technological issues. We show that the similar to 4X power advantage that ideal on-chip global optical interconnects have been projected to have is reduced to null when the power required for thermal regulation of critical optical components alone are added into the calculations. We also discuss latency, spatial bandwidth, polarization and a host of other technological issues and reassess the benefits of dense on-chip optical interconnects for dense global routing.