Evaluating the Practicability of Error-Detection Circuit Exposed to Single-Event Upsets in 65 nm CMOS Technology

This paper presents a multiple NAND gate error-detection module for diagnosing single-event effects (SEEs) in the combinational logic circuits which fabricated in 65 nm technology. The proposed approach evaluates the SEUs propagate effects by using device TCAD and circuit mixed simulation, which is derived based on device physics and fault sensitizing access propagate methods. Simulation results show that this circuit design can verify which module has SEU disturbances in the input electrodes, and it provides an effective tolerant method for soft-errors in the insensitive signal period. The circuit does not incur significant area or speed degradation on the chip.