A new analytical delay and noise model for on-chip RLC interconnect

被引：13

作者：

Cao, Y ^{[1
]}

Huang, XJ ^{[1
]}

Sylvester, D ^{[1
]}

Chang, N ^{[1
]}

Hu, CM ^{[1
]}

机构：

[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年

关键词：

D O I：

10.1109/IEDM.2000.904444

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we develop a 2(nd) order distributed RLC waveform model that captures both delay and overshoot effects more accurately than previous 1(st) order models. We then present a new approach to decoupling a set of coupled RLC lines by examining current return paths. Noise and delay results from this technique match SPICE for a wide range of input parameters.

引用

页码：823 / 826

页数：4

共 4 条

[1]

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