Implementation of a FFT/IFFT module on FPGA:: Comparison of methodologies

被引：0

作者：

Viejo, J. ^{[1
]}

Millan, A. ^{[1
]}

Bellido, M. J. ^{[1
]}

Ostua, E. ^{[1
]}

Ruiz-de-Clavijo, P. ^{[1
]}

Munoz, A. ^{[1
]}

机构：

[1] Univ Seville, ETS Ing Informat, Dept Elect Technol, Grp ID2 Invest & Desarrollo Digital, E-41012 Seville, Spain

来源：

2008 4TH SOUTHERN CONFERENCE ON PROGRAMMABLE LOGIC, PROCEEDINGS | 2008年

关键词：

D O I：

10.1109/SPL.2008.4547724

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this work, we have compared three different methodologies for the implementation of a FFT/IFFT module on FPGA: VHDL coding (VC), System-level tools at RT level (STR), and System-level tools at macroblock level (STM). In terms of resource usage and operation frequency, STM has obtained interesting results, although it has an important restriction about internal data width which produces a mean output error of 2.1%. VC and STR become a more general alternative that yields to a lower mean error (1.0%). Thus, we propose to combine VC and STR in order to facilitate the design process as well as allow designers to maintain total control over the module internal architecture and obtain an efficient structure.

引用

页码：7 / 11

页数：5