Development of fully FPGA-based 3D (X, Y, t) detection systems using multi-channel Tapped-Delay-Line Time-to-Digital Converter with Cross Delay-Line detectors

被引：0

作者：

Lusardi, N. ^{[1
]}

Garzetti, F. ^{[1
]}

Geraci, A. ^{[1
]}

Cautero, G. ^{[2
]}

Dri, C. ^{[2
]}

Pittana, P. ^{[2
]}

Sergo, R. ^{[2
]}

Stebel, L. ^{[2
]}

机构：

[1] Politecn Milan, DEIB, Via Golgi 40, I-20133 Milan, MI, Italy

[2] Elettra Sincrotrone Trieste, SS 14,Km 163,5 AREA Sci Pk, I-34149 Trieste, Italy

来源：

2017 IEEE NUCLEAR SCIENCE SYMPOSIUM AND MEDICAL IMAGING CONFERENCE (NSS/MIC) | 2017年

关键词：

PROBE;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Time-resolved experiments often need detection devices able to provide information about position and arrival time of each detected event. Time resolution is a fundamental requirement for these devices, along with the high versatility and fast real-time computing of the acquisition system. Typical architectures, based on Time-to-Digital Converters (TDC) followed by a FPGA, combine very fast parallel computing with a time precision better than hundreds of picoseconds, allowing to perform state-of-the-art time-resolved experiments. Nevertheless, time resolution is still a limiting factor, in particular for imaging applications where the detector spatial resolution is determined through time measurement. Furthermore, the separation between the TDC devices and a readout FPGA has some drawbacks in terms of versatility of the system. In this article, we present a new approach, combining FPGA-based multi-channel Tapped-Delay-Line TDC and an efficient multipurpose readout logic, to greatly improve the overall performance and versatility of Cross Delay-Line (CDL) detector systems.

引用

页数：4