Modelling and characterisation of the input I-V curves of bipolar JFET structures showing a negative resistance behaviour

被引：4

作者：

Bellone, S

Daliento, S

Sanseverino, A ^{[1
]}

机构：

[1] Univ Naples Federico II, Dept Elect Engn & Telecommun, I-80125 Naples, Italy

[2] Univ Salerno, Dept Informat & Elect Engn, I-84084 Fisciano, Italy

来源：

SOLID-STATE ELECTRONICS | 2001年 / 45卷 / 03期

关键词：

modelling; negative resistance devices; bipolar JFET devices;

D O I：

10.1016/S0038-1101(00)00252-5

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An analytical model of the I-V input curves of normally on JFET structures for an arbitrary drain voltage is proposed. The model is capable to predict the occurrence of a negative resistance in the curves in agreement with numerical simulations and experiments. It is shown that, similarly to the unijunction transistor, the negative resistance is determined by the variation of the ohmic drain voltage occurring in the base as the gate voltage reaches the onset value of the conductivity modulation regime. Moreover the model can be considered the basic theory of the experimental method proposed [Solid-State Electron 43(7) (1999) 1201] for measuring the series resistance of lateral diodes. (C) 2001 Elsevier Science Ltd. All rights reserved.

引用

页码：483 / 488

页数：6

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