Accurate timing analysis by modeling caches, speculation and their interaction.

被引：10

作者：

Li, XF ^{[1
]}

Mitra, T ^{[1
]}

Roychoudhury, A ^{[1
]}

机构：

[1] Natl Univ Singapore, Sch Comp, Singapore 117543, Singapore

来源：

40TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2003 | 2003年

关键词：

worst case execution time; cache; branch prediction;

D O I：

10.1109/DAC.2003.1219046

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

Schedulability analysis of real-time embedded systems requires worst case timing guarantees of embedded software performance. This involves not only language level program analysis, but also modeling the effects of complex micro-architectural features in modern processors. Speculative execution and caching are very common in current processors. Hence one needs to model the effects of these features on the Worst,Case Execution Time (WCET) of a program. Even though the individual effects of these features have been studied recently, their combined effects have not been investigated. We do so in this paper. This is a non-trivial task because speculative execution can indirectly affect cache performance (e.g., speculatively executed blocks can cause additional cache misses). Our technique starts from the control flow graph of the embedded program, and uses integer linear programming to estimate the program's WCET. The accuracy of our modeling is illustrated by tight estimates obtained on realistic benchmarks.

引用

页码：466 / 471

页数：6